In the ASIC design cycle, deep submicron technologies required sound approach for complex SoC designs. This efficiency is critical for a quick turnaround time, and if it succeeds on the first try, it will result in a shorter time to market by achieving with high reliability and yield. The only way to achieve first-time success is to use a precise testing approach. BroadSemi Company has good experience with lower technology nodes in the design for testing arena and skill in managing diverse testing methods give us the benefit of perfect testing for any complex SoC Design.

OUR DFT SERVICES INCLUDE:

• Design Scan Architecture
• Memory BIST and LBIST insertion
• Boundary Scan insertion and JTAG IEEE1149.1/IJTAG 1687
• Test Pattern generation & simulation validation
• Coverage Analysis & improvement
• Post Silicon Debugging

Our DFT Capabilities

• Quality of design & library check assurance
• Creating the required automation utilities/scripts based on the customer needs and also provide complete Test execution plan & Methodology.
• DFT CHECKS: Sub-chip level Scan-Insertion, Sub-chip level MBIST insertion and formal equivalence, Fault-coverage analysis, ATPG and MBIST pattern verification at the sub-chip level, Top-Level (Boundary Scan) generation, Sub-chip integration, and DFT violation check.

• Interacting with Logic & Physical team for DFT closure
• Performing gate level simulations with no timing/timing.
• Final ATE Tester format generation
• Our team supports all major vendor tools such as Mentor Tessent, Synopsys, Cadence.